1. Field of the Invention
The field of the present invention relates generally to dynamic random access memories (DRAMs), and more specifically to a process for making a nitride cap on the oxide collar in a DRAM cell.
2. Description of the Prior Art
Dynamic random-access memory (DRAM) cells are composed of two main components, a storage capacitor (which stores charge) and an access transistor (which transfers charge to and from the capacitor). The communication between the storage capacitor and the access transistor is controlled by a select signal (commonly referred to as a word line) which connects one plate of the capacitor to a data line (commonly referred to as the bit line). The storage capacitor is typically located in a deep trench which is etched into a semiconductor substrate. This trench design has become the standard in DRAM processing, since it enables a greater amount of charge to be stored in a small area without taking up chip surface area.
Conventional DRAM arrays are organized so that multiple storage cells are positioned as close as possible to one another. During the operation of the array, individual storage cells are selected by the energizing of the word line, each of the selected cells communicating their contents to sense amplifiers by way of the associated bit lines. In order for the DRAM array to function properly, it is essential to isolate one transistor from a neighboring transistor, and each individual transistor from other active components. Since current research is directed toward a greater density of storage cells per unit area of semiconductor substrate, effective isolation means becomes all the more important.
Current technology provides for the isolation of individual transistors in the form of a trench isolation region wherein a vertical area is etched into the electrically active silicon substrate and filled with oxide. This area is generally referred to in the art as the shallow trench isolation (STI). In trench capacitor DRAM technology, the isolation of individual transistor components from other active areas, on the other hand, is accomplished by an oxide collar. This oxide collar surrounds the upper part of each individual trench, preventing vertical parasitic leakage between the buried plate and the connection of the inner trench electrode to the transfer device. There are a number ways in which this isolation may be accomplished, all commonly using insulating layers of SiO.sub.2 or some other inert material as the collar. The thickness of this collar can be varied, and is typically designed so as to effectively prevent voltage on an interconnection line above the insulator from inverting the silicon beneath the insulator and thereby creating a parasitic channel.
A major problem that exists in conventional trench capacitors, which allows for vertical parasitic leakage between the buried plate and the connection of the inner trench electrode, is oxidation induced stress that is built up in the oxide collar during the fabrication processes of the DRAM. During these oxidation steps, oxygen can diffuse from the surface of the silicon substrate into and along the oxide collar. The neighboring silicon substrate and the trench polysilicon fill can therefore become oxidized. This oxidation leads to a tapered expansion of the collar oxide, which, in turn, leads to a high stress level in the silicon substrate and to the generation of extended crystal defects in the silicon substrate. The defects manifest themselves as dislocations or stacking faults, and are especially prevalent around the most expanded part of the oxide collar. The resulting stress in the silicon substrate, coupled with the extended crystal defects, can cause electrical leakage across the junctions of the associated transistor.
A schematic drawing of a 256 Mb trench DRAM cell equipped with a conventional oxide collar is depicted in FIG. 1. The structure consists of a trench capacitor 10 which is etched into a single crystal P type doped silicon substrate 16. The lower level of the trench 12 is typically filled with an N+ doped polysilicon material which is isolated from the buried N-well by an insulating node dielectric barrier 14. The storage node 24 of the capacitor in the trench is typically formed from highly doped N+ polysilicon and is connected to the DRAM's word line 20 by a self-aligned buried strap 22. The DRAM also has a shallow trench isolation (STI) region 28 which isolates this cell from adjacent cells. The DRAM cell includes a bit line 17 which runs horizontally connecting the cell's bit line contact 19 to other cell' bit line contacts. One of the DRAM's word lines forms the pass gate 13 to an adjacent cell. A second array word line 15 runs vertically, passing over the trench capacitor 10 and partially over a shallow trench isolation (STI) region 28, forming pass gates for other adjacent cells.
As can be inferred from FIG. 1 which shows a prior art 256 Mb DRAM cell, stress in the region 23 between the oxide collar 18 and the highly doped single crystal substrate material 16 can cause the region to be susceptible to parasitic leakage. In order to prevent this leakage, it is first desirable to cure the underlying cause that produces it, namely, to block the oxygen diffusion into the oxide collar. A possible solution which would substantially prevent this problem would be to isolate the trench by covering it with a cap or mask that is impervious to oxygen (such as a nitride liner). Such an electrically inert liner could act as a diffusion barrier for oxygen and would therefore block the diffusion path into the oxide collar without adversely affecting the performance of the DRAM.
Attempts have been made in the prior art to address this need for masks or liners that prevent oxygen diffusion from the substrate surface into the underlying trench structure. For example, U.S. Pat. No. 4,922,313 entitled "PROCESS FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND PRODUCT FORMED THEREBY" issued to O. Tsuchiya and assigned to Hitachi, Ltd., describes DRAM structure in which a silicon nitride layer is used as an oxidation mask for local oxidation along the deep trench capacitor sidewall. The intention of this particular nitride mask, however, is to define an area of electrical connection between the polysilicon trench fill and the substrate. The mask is completely removed in subsequent processing steps.
Another invention that utilizes a silicon nitride liner in a deep trench DRAM structure is disclosed in U.S. Pat. No. 5,406,515 entitled "METHOD FOR FABRICATING LOW LEAKAGE SUBSTRATE PLATE TRENCH DRAM CELLS AND DEVICES FORMED THEREBY" issued to T. V. Rajeevakumar and assigned to the International Business Machines Corporation. The invention describes a low leakage DRAM cell in which a silicon nitride masking layer is used as a diffusion mask for dopant outdiffusion into vertical parts of the deep trench. The silicon nitride liner in this invention is deposited vertically along the deep trench and does not function to reduce oxidation-induced stress during the processing of the device.
While these and other masking liners have been used as diffusion barriers in DRAM devices, there are still several major disadvantages associated with prior art technology. If, for example, the nitride liner is deposited too thin, it is permeable to diffusing oxygen and therefore does not act as an effective barrier. If, on the other hand, the nitride liner is deposited too thick, subsequent etching steps (that occur, for example, during the pad nitride strip) severely damage the liner exposing gaps in the liner. Such gaps are detrimental in further etching steps, allowing the etchants to attack the underlying oxide structure resulting in an unacceptably large void in the oxide fill of the shallow trench isolation region. Still another disadvantage to prior art nitride liners is that electrical charge trapped in the SiN liner or at the interface to the neighboring oxide layers can lead to parasitic leakage along the surface of the shallow trench isolation.
It is, therefore, an object of the present invention to provide an improved method for blocking oxygen diffusion into the oxide collar of a DRAM cell which overcomes the problems associated with prior art techniques.